1. Field of the Invention
The present invention relates to an amplifying circuit including a bias circuit, and more particularly, to bias circuits for making the characteristics of a plurality of amplifying transistors coincide.
In the case of a balanced amplifier in which an input is divided into two branches which are respectively amplified by amplifying transistors such as field effect transistors (herein after referred to as FETs), and the outputs thereof are combined to obtain a desired output, or in the case of supervising an input level of a mixer by dividing the output of the balanced amplifier into two branches, one of which is input into the mixer for effecting a frequency conversion and the other of which is measured, it is necessary to coincide the output power of the two FETs. The adjustment for this is effected by setting the drain voltages V.sub.DS and the drain currents I.sub.D of the FETs.
To achieve this effect, a bias circuit is desired in which the drain currents I.sub.D can be kept constant and the drain voltages V.sub.DS can be changed independently from the drain currents I.sub.D, and the number of adjusting points is kept as small as possible.
2. Description of the Related Art
In a conventional balanced amplifier, the drain current and the drain voltage of each FET are respectively adjusted by variable resistors, however, there are problems in that a large number of expensive variable resistors are necessary and the adjustment of the drain currents is troublesome, as later described in more detail with reference to the drawings.
In another conventional balanced amplifier, the drain current and the drain voltage of each FET are automatically determined by employing a bias transistor. In this case, however, the drain voltage cannot be determined independently from the determination of the drain current, as later described in more detail with reference to the drawings.